Senior FPGA Design Engineer at Aegis Technologies in Albuquerque, NM
Overview Being on the BlueHalo Team means working alongside the brightest minds in technology on the toughest challenges facing our nation - not just every once in a while, but every single day. Together, we are leading the transformation of modern warfare and each BlueHalo employee plays a key role. That's why our investment in you goes beyond a rewarding salary and benefits package. We're committed to providing our people with the best opportunities to develop their skills, share their knowledge, and push their innovative ideas to the cutting edge. Having fun doing it with a team that feels like family all across BlueHalo nation is the ultimate park. From Space and Directed Energy to Cyber and Intelligence to C4ISR and Air & Missile Defense, there is no limit to where you can take your career with us. Are you ready to launch a career at BlueHalo? Responsibilities
Summary:
BlueHalo is looking for a dynamic Sr. FPGA Design Engineer to support our Laser Communications team. BlueHalo is purpose-built to provide industry-leading capabilities in the domains of Space Superiority and Directed Energy, Air and Missile Defense and Command, Control, Communications, Computers, Intelligence, Surveillance, and Reconnaissance (C4ISR), and Cyber and Intelligence. Help us architect and build what could become the ubiquitous standard for free space laser communications. We will need all your experience and creativity related to networking and signal processing targeting FPGA design! Primary Roles and
Responsibilities:
Provides constructive input to peer reviews of others designs. Participates in peer reviews and receives constructive feedback of his/her designs Develops synthesizable RTL in VHDL or (System)Verilog based on a model or specification Becomes intimately familiar with the model such that he/she can provide feedback where necessary to the model developer on problems or gaps in the model implementation Helps board designers with pin planning and other FPGA related considerations Teaches the rest of the team about effective FPGA design techniques that may concern them. For example, the design engineer will provide feedback on the verification engineers test plan. He/she will coach the automation/infrastructure engineer on how best to automate the use of the synthesis tools. Writes suitable XDC constraints for FPGA synthesis and may perform manual floor planning when necessary Work Environment This job operates in professional/secure office & laboratory environment. This position routinely uses standard office equipment such as computers, phones, photocopiers, filing cabinets, fax machines and other equipment as needed. Position Type/Expected Hours of Work This is a full-time position. Days and hours of work are nominally Monday through Friday, 8 a.m. to 5 p.m. Travel Travel is primarily local during the business day, although some out-of-area and overnight travel will be required. Primary Location:
Albuquerque, NM. Relocation Available:
Yes Qualifications Required Qualifications and Skills:
Bachelor of Science in EE, CS, or related field from accredited university 5
years of experience doing modern HDL design (VHDL/SystemVerilog) Positive experience working within a collaborative, distributed, team environment Solid understanding of FPGA synthesis tools (Vivado/Quartus) and details such as pin planning, clock crossing, and timing closure Solid understanding of hardware testing and debug techniques Knowledgeable in the different resources and primitives available in the target FPGA technology Understands complexity analysis for trades in algorithm area and performance Highly skilled in using and implementing low level protocols such as AXI4, AXI4-streaming, SPI, etc. Understands how/when to use vendor provided IP cores Experience with GIT Good written and verbal communication skills; able to communicate complex algorithms and methods both verbally and in documentation S. Citizen able to obtain and maintain a U.S. Department of Defense (DoD) security clearance Desired Qualifications and Skills:
Master of Science in EE, CS, or equivalent field HDL simulation/verification experience targeting SystemVerilog; familiarity with industry standard HDL simulation tools Knowledgeable in various modern high-level synthesis (HLS) techniques, and understands the trades associated with using HLS in a complex team project Working knowledge of MATLAB/Simulink, Python, or C+
Experience developing HDL based Ethernet networking algorithms Knowledge of signal processing, optical communications, or forward-error correction algorithms Understanding of hardware-software interfaces Understanding of and experience using test driven development (TDD) Previous experience in the aerospace or defense industries Experience preparing and executing integration test procedures and supporting integration into a larger system architecture Understanding of quality assurance methodologies and best practices for high-reliability systems for space-flight applications
Salary Range:
$80K -- $100K
Minimum Qualification
Electrical Engineering, Hardware DevelopmentEstimated Salary: $20 to $28 per hour based on qualifications.
Summary:
BlueHalo is looking for a dynamic Sr. FPGA Design Engineer to support our Laser Communications team. BlueHalo is purpose-built to provide industry-leading capabilities in the domains of Space Superiority and Directed Energy, Air and Missile Defense and Command, Control, Communications, Computers, Intelligence, Surveillance, and Reconnaissance (C4ISR), and Cyber and Intelligence. Help us architect and build what could become the ubiquitous standard for free space laser communications. We will need all your experience and creativity related to networking and signal processing targeting FPGA design! Primary Roles and
Responsibilities:
Provides constructive input to peer reviews of others designs. Participates in peer reviews and receives constructive feedback of his/her designs Develops synthesizable RTL in VHDL or (System)Verilog based on a model or specification Becomes intimately familiar with the model such that he/she can provide feedback where necessary to the model developer on problems or gaps in the model implementation Helps board designers with pin planning and other FPGA related considerations Teaches the rest of the team about effective FPGA design techniques that may concern them. For example, the design engineer will provide feedback on the verification engineers test plan. He/she will coach the automation/infrastructure engineer on how best to automate the use of the synthesis tools. Writes suitable XDC constraints for FPGA synthesis and may perform manual floor planning when necessary Work Environment This job operates in professional/secure office & laboratory environment. This position routinely uses standard office equipment such as computers, phones, photocopiers, filing cabinets, fax machines and other equipment as needed. Position Type/Expected Hours of Work This is a full-time position. Days and hours of work are nominally Monday through Friday, 8 a.m. to 5 p.m. Travel Travel is primarily local during the business day, although some out-of-area and overnight travel will be required. Primary Location:
Albuquerque, NM. Relocation Available:
Yes Qualifications Required Qualifications and Skills:
Bachelor of Science in EE, CS, or related field from accredited university 5
years of experience doing modern HDL design (VHDL/SystemVerilog) Positive experience working within a collaborative, distributed, team environment Solid understanding of FPGA synthesis tools (Vivado/Quartus) and details such as pin planning, clock crossing, and timing closure Solid understanding of hardware testing and debug techniques Knowledgeable in the different resources and primitives available in the target FPGA technology Understands complexity analysis for trades in algorithm area and performance Highly skilled in using and implementing low level protocols such as AXI4, AXI4-streaming, SPI, etc. Understands how/when to use vendor provided IP cores Experience with GIT Good written and verbal communication skills; able to communicate complex algorithms and methods both verbally and in documentation S. Citizen able to obtain and maintain a U.S. Department of Defense (DoD) security clearance Desired Qualifications and Skills:
Master of Science in EE, CS, or equivalent field HDL simulation/verification experience targeting SystemVerilog; familiarity with industry standard HDL simulation tools Knowledgeable in various modern high-level synthesis (HLS) techniques, and understands the trades associated with using HLS in a complex team project Working knowledge of MATLAB/Simulink, Python, or C+
Experience developing HDL based Ethernet networking algorithms Knowledge of signal processing, optical communications, or forward-error correction algorithms Understanding of hardware-software interfaces Understanding of and experience using test driven development (TDD) Previous experience in the aerospace or defense industries Experience preparing and executing integration test procedures and supporting integration into a larger system architecture Understanding of quality assurance methodologies and best practices for high-reliability systems for space-flight applications
Salary Range:
$80K -- $100K
Minimum Qualification
Electrical Engineering, Hardware DevelopmentEstimated Salary: $20 to $28 per hour based on qualifications.
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